1. Field of the Invention
The invention generally relates to estimating test yields for semiconductor products. More particularly, the invention relates to estimating a test yield for a semiconductor product that can be created from multiple library elements based on a critical area analysis of each of the library elements, an estimation of library-element-to-library-element shorting and an estimation of product-level wiring faults sensitivity.
2. Description of the Related Art
Many semiconductor products and, particularly, application specific integrated circuits (ASICs), are formed by combining pre-designed units (i.e., integrated circuit library elements) that are organized by circuit type. Each prefabricated unit or library element includes a set of integrated circuit devices that are wired together so that they perform a specific function. Currently, critical area analysis techniques (e.g., techniques based on dot-throwing, geometric expansion, Voronoi diagrams, etc.) are used to accurately estimate test yield loss in semiconductor products. These techniques are used to estimate test yield loss caused by sensitivity to random defects and, typically, are only performed after a product design layout is completed, for example, by performing analysis on the final merged physical design data for the product. However, current methods for estimating product test yield prior to product design layout, which predict test yield based on product size and/or circuit, gate or pin counts, are not as accurate. Thus, oftentimes pre- and post-product design layout test yield estimates are not the same. Since product cost estimates and/or quotes based on test yield estimates are generally provided to a customer before the design of a product is set out, a method is needed to provide a more accurate pre-product design layout test yield estimate.